/*
 Bug ID:0003;
 Origin: me
 Version: 0.2b candidate
 Symptom: infinite loop at inout port (the values from inside and outside
                   are switched over and over..)
 Fixing status: now
*/

module cucu;
 wire w;
 reg r;

 mnm m (w);

 initial begin
  r = 0;
  #3;
 end

endmodule


module mnm(io);
 inout io;
 wire io;

 reg rio;
 
 assign io = rio;
 
 initial begin
   rio = 'bz;
   #1;
   rio = 1;
 end

endmodule
